搜索资源列表
lab_simulation
- verilog 开发的，模拟CPU流水线操作的工程设计。-verilog developed to simulate the engineering design of CPU pipelining.
xcv
- 本代码是一个利用D3D固定流水线和可编程流水线一起使用的一个粒子。进入之后是一个3D场景，天空盒还加了动态纹理效果。程序中还加入了一个小球，按下1键后，可模拟抛物线运动。-This code is a fixed-line and programmable using D3D for use with a particle line. Followed by a 3D scene into the sky box also added a dynamic texture. Program al
daobao
- 基于PCL-812PG采集卡的开关量通道，实现模拟流水线打包机工作过程的c代码。-PCL-812PG acquisition card based on the digital channel for analog line packer working process of the c code
FastDLX
- FastDLX模拟器是一个用C语言编写的，结构精简、功能全面的DLX模拟器，除了模拟DLX流水线的全部功能外，它还能够模拟分离的指令Cache和数据Cache的行为。-FastDLX is a DLX monitor
Tomasulo
- Tomasulo模拟器，系统结构流水线的乱序执行模拟-Tomasulo simulator, system architecture simulated order execution pipeline
fg
- 根据流水线作业的原理，模拟饮料装配过程。-According to the principle of pipeline operations, simulated beverage assembly process.
simulation-software
- 系统结构课程的实验模拟软件。寄存器，流水线，时序等实验都可以做，支持代码编辑。-Experimental simulation software of the system architecture courses. Register, pipelining, timing and other experiments can be done to support the code editor.
RISC_CPU
- 一个32位流水线 CPU 设计， 含设计文档和模拟图。-A 32-bit pipelined CPU design, including design documentation and simulation in Fig.
zidongjishu.zip
- 基于stc51单片机实现模拟流水线上自动计数功能！,Automatic counting function pipeline analog based on stc51 microcontroller!
dlxview-win
- 一个模拟流水线的模拟器，可以完成记分牌算法以及tomsuolo算法。可以判断运行前后的优劣-An analog simulator pipeline can be completed scoreboard algorithm tomsuolo algorithm. Can judge run before and after the pros and cons
renderTestAPP
- 基于DX9的一个渲染程序，模拟实现了DX渲染流水线，使用点绘制操作封装了各种光栅化函数，最后通过自定义的流水线实现了3D绘制效果。压缩包里带有一定的说明文档。-DX9-based rendering of a program to simulate achieve a DX rendering pipeline, using the dot drawing operations encapsulate various rasterization functions, and finally th
WINDLX
- WINDLX模拟器，可用于模拟指令流水线-WINDLX simulator can be used to simulate the instruction pipeline
1
- 实现dlx五级流水线的lw sw addi subi multi等指令功能 ，在modelsim软件环境下仿真模拟实现。-Achieve dlx five pipeline lw sw addi subi multi other command functions, in modelsim simulation software environment to achieve.
cpu_design
- FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
pro1
- 电子科技大学计算机系统结构课程设计：模拟流水线指令调度-Design: Analog line instruction scheduling
RISC-CPU
- 精简指令集 16位流水线CPU 可实现硬件模拟-16-bit pipelined RISC CPU hardware emulation can be achieved
My_CPU_and_Memory_System_Design
- 实现内存到Cache的直接映射模拟，利用串行执行方式实现五级流水线。(The direct mapping simulation of memory to Cache is realized, and five level pipelining is realized by serial execution.)